1. Field Of The Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for the intelligent sequentially programming of memory cells in a flash electrically-erasable programmable read only memory (flash EEPROM) array in order to reduce the current and power utilized and to increase the speed of operation.
2. History Of The Prior Art
This application is a continuation-in-part of U.S. patent application Ser. No. 08/119,520 entitled, Method and Apparatus For Sequential Programming of the Bits in a Word of a Flash EEPROM Memory Array, E. Larson and J. Javanifard, filed Sep. 10, 1993, and assigned to the assignee of the present invention. There has been a recent trend toward lowering the power requirements of portable computers. In order to reduce power consumption, much of the integrated circuitry used in personal computers is being redesigned to run at low voltage levels. The circuitry and components used in portable computers are being designed to operate at voltage levels such as 5 volts and 3.3 volts in order to use less current. This helps a great deal to reduce the power needs of such computers.
However, some of the features of portable computers require higher voltages. Recently, flash electrically-erasable programmable read only memory (flash EEPROM memory) has been used to store BIOS processes.
This memory may be erased and reprogrammed without removing the BIOS circuitry from the computer by running a small update program when the BIOS processes are changed. Other versions of flash EEPROM memory are being used for long term storage in place of electro-mechanical hard disk drives. However, erasing and reprogramming flash EEPROM memory typically requires approximately twelve volts to accomplish effectively; and the lower voltage batteries provided in portable computers, in general, are not capable of furnishing this voltage with sufficient current to accomplish the operations.
Typically, charge pump circuits have been used to provide a high voltage from a lower voltage source. However, the positive source method of erasing flash EEPROM memories draws a very substantial amount of current. Similarly, programming such arrays using traditional techniques has required large amounts of current. Charge pumps furnishing such voltages with sufficient current typically utilize large capacitors which require a large amount of die space. Recently it has been discovered that using specially designed charge pumps sufficient current can be generated to accomplish positive source erase and the programming of flash EEPROM memory arrays. A charge pump arrangement for accomplishing positive source erase is disclosed in detail in U.S. patent application Ser. No. 08/119,423, entitled Method And Apparatus For A Two Phase Bootstrap Charge Pump, K. Tedrow et al, filed on Sep. 10, 1993, and assigned to the assignee of the present invention.
It is still desirable, even using advanced charge pumps, to reduce the amount of current used in programming flash EEPROM memory arrays.
A flash EEPROM memory array is made up of memory cells which include floating gate field effect transistor devices. The N type memory transistors may be programmed by storing a negative charge on the floating gate. A negative charge on the floating gate shifts the threshold voltage of the memory transistor making it less conductive. The condition of the memory transistors (programmed or erased) may be detected by interrogating the cells and sensing whether current flows or not. The programming of memory cells is typically accomplished a word at a time but conventionally requires that the drain of selected cells be placed at six or seven volts, the gate at eleven or twelve volts, and the source at ground. This programming operation draws substantial current because the gate terminal is raised above the level of the drain and source terminals while a significant potential difference is placed between the drain and source terminals.
The simultaneous programming of each bit of a sixteen bit word requires approximately one milliampere of current so that programming one word draws approximately sixteen milliamperes. The peak current drawn during the conventional programming operation may be as high as forty milliamperes. This is a very large amount of current and requires larger charge pumps with larger capacitances which require a large amount of die space and therefore tend to increase rather than decrease the size of components used in portable computers. Moreover, integrated circuit charge pumps cannot be made to operate as efficiently as can stand alone charge pumps because they do not make use of elements such as inductors which maximize efficiency. In fact, such charge pumps operate at efficiencies of approximately forty percent so that, for example, seventy-two milliamperes of peak current are required to supply the sixteen milliamperes necessary for programming a word.
For this reason, apparatus and methods which reduce current requirements for programming flash EEPROM memory arrays are very desirable.